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SRDA3.3 ? 4
ESD Protection of Power Supply Lines
When using diodes for data line protection, referencing to
a supply rail provides advantages. Biasing the diodes reduces
their capacitance and minimizes signal distortion.
Implementing this topology with discrete devices does have
disadvantages. This configuration is shown below:
L di ESD /dt factor. A relatively small trace inductance can result
in hundreds of volts appearing on the supply rail. This
endangers both the power supply and anything attached to
that rail. This highlights the importance of good board layout.
Taking care to minimize the effects of parasitic inductance
will provide significant benefits in transient immunity.
Power
Supply
V CC
I ESDpos
Even with good board layout, some disadvantages are still
present when discrete diodes are used to suppress ESD events
across datalines and the supply rail. Discrete diodes with good
transient power capability will have larger die and therefore
Protected Data Line
Device
D1
D2
I ESDpos
I ESDneg
VF + V CC
I ESDneg
higher capacitance. This capacitance becomes problematic as
transmission frequencies increase. Reducing capacitance
generally requires reducing die size. These small die will have
higher forward voltage characteristics at typical ESD
transient current levels. This voltage combined with the
smaller die can result in device failure.
Figure 6.
? VF
The ON Semiconductor SRDA3.3 ? 4 was developed to
overcome the disadvantages encountered when using discrete
diodes for ESD protection. This device integrates a TVS
Looking at the figure above, it can be seen that when a
positive ESD condition occurs, diode D1 will be forward
diode within a network of steering diodes.
biased while diode D2 will be forward biased when a negative
ESD condition occurs. For slower transient conditions, this
D1
D3
D5
D7
system may be approximated as follows:
For positive pulse conditions:
Vc = V CC + Vf D1
D2
D4
D6
D8
For negative pulse conditions:
Vc = ? Vf D2
ESD events can have rise times on the order of some
number of nanoseconds. Under these conditions, the effect of
parasitic inductance must be considered. A pictorial
representation of this is shown below.
0
Figure 8. SRDA3.3 ? 4 Equivalent Circuit
During an ESD condition, the ESD current will be driven
Power
Supply
V CC
I ESDpos
to ground through the TVS diode as shown below.
Power
Supply
Protected
Device
Data Line
D1
I ESDpos
I ESDneg
V CC
D1
I ESDpos
D2
V C = V CC + Vf + (L diESD/dt)
I ESDneg
Protected
Device
Data Line
D2
V C = ? Vf ? (L diESD/dt)
Figure 7.
An approximation of the clamping voltage for these fast
transients would be:
For positive pulse conditions:
Vc = V CC + Vf + (L di ESD /dt)
For negative pulse conditions:
Vc = ? Vf – (L di ESD /dt)
As shown in the formulas, the clamping voltage (Vc) not
only depends on the Vf of the steering diodes but also on the
Figure 9.
The resulting clamping voltage on the protected IC will
be:
Vc = V FD1 + V TVS .
The clamping voltage of the TVS diode is provided in
Figure 2 and depends on the magnitude of the ESD current.
The steering diodes are fast switching devices with unique
forward voltage and low capacitance characteristics.
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